DocumentCode
581014
Title
Ultra-low power NEMS FPGA
Author
Han, Sijing ; Sirigiri, Vijay ; Saab, Daniel G. ; Tabib-Azar, Massood
Author_Institution
EECS, Case Western Reserve Univ., Cleveland, OH, USA
fYear
2012
fDate
5-8 Nov. 2012
Firstpage
533
Lastpage
538
Abstract
In this paper, we discuss a new type of NEMS switches that can be configured to implement any 2-input logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT) in a single device structure. These devices can be used to implement FPGA where a four-input CLB requires only nine NEMS switches and at most two mechanical delays per computation. In contrast, CMOS CLBs require 150 traditional switches. By reducing the number of devices, our approach improves yield, reproducibility, speed, power and simplifies implementation.
Keywords
field programmable gate arrays; logic gates; low-power electronics; microswitches; nanoelectromechanical devices; 2-input logic gates; AND gate; CMOS CLB; NAND gate; NEMS switches; NOR gate; NOT gate; OR gate; XNOR gate; XOR gate; single device structure; ultralow power NEMS FPGA; Bridge circuits; CMOS integrated circuits; Field programmable gate arrays; Logic gates; Nanoelectromechanical systems; Resistors; Routing; Embedded system; FPGA; NEMS; design;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Type
conf
Filename
6386722
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