Power grid effects and their impact on-die

This paper is intended to give a brief tutorial understanding of on-die power grid effects. Board, package and on-die power grids deliver power to a die having both global (full-die) as well as local (intra-die) transient effects. With a simple excitation model and a detailed die/package/board model, one can come to understand the dynamic effects occurring inside the die in terms of global and local voltage droop scenarios. These effects have been confirmed by measurements on-die. However, a simple excitation model is usually not representative of the worst-case transient scenarios causing the largest voltage droop. Any chip, especially a microprocessor, contains so many potential state transitions that it is not possible to simulate or enumerate all of them. A spectral-based learning and optimization method can alleviate this problem pre-silicon, while a micro-architectural based test generation scheme can help alleviate the problem post silicon.