Title :
Fast approximation for peak power driven voltage partitioning in almost linear time
Author :
Wang, Jia ; Chen, Xiaodao ; Liu, Lin ; Hu, Shiyan
Author_Institution :
Dept. of Electr. & Comput. Eng., Michigan Technol. Univ., Houghton, MI, USA
Abstract :
Voltage partitioning on functional units/blocks targeting peak power minimization has been demonstrated to be effective for energy reduction considering voltage island shutdown impact. However, the existing technique can only solve this NP-hard problem efficiently on small designs. In this paper, a much faster linear time approximation scheme is proposed, which can approximate the optimal voltage partitioning solution within a factor 1 + ϵ, for any 0 <; ϵ <; 1, and runs in O(n + 1/ϵO(1)) time, where n is the number of functional units. There are multiple ingredients in such a surprisingly low time complexity algorithm. It first categorizes all the functional units into big functional units and small functional units using an ϵ related threshold. Subsequently, a rounding based dynamic programming procedure is performed to handle big functional units and a linear programming based algorithm is performed to handle small functional units, which is followed by the discretization of the continuous linear programming solution. Moreover, through the exploration of the unique nature of our problem, a greedy algorithm is proposed to optimally solve the linear programming formulation in a combinatorial fashion. Further, since patching a salient partitioning solution of big functional units with that of small functional units could lead to a much worse combined solution, a highly efficient enumeration process running in time independent of n is proposed. The experimental results demonstrate that our algorithm runs very fast. It needs only 0.3 second to partition a testcase with 5000 functional units which is more than 10000 X faster than the existing algorithm while still reducing the peak power by 7.4%.
Keywords :
VLSI; circuit complexity; dynamic programming; greedy algorithms; integrated circuit design; linear programming; NP-hard problem; combinatorial fashion; continuous linear programming solution; energy reduction; functional units/blocks; greedy algorithm; linear time approximation scheme; optimal voltage partitioning solution; peak power driven voltage partitioning; peak power minimization; rounding based dynamic programming procedure; salient partitioning solution; time complexity algorithm; voltage island shutdown impact; Approximation methods; Capacitance; Dynamic programming; Greedy algorithms; Heuristic algorithms; Linear programming; Partitioning algorithms; Energy Efficiency; Linear Time Approximation Scheme; Peak Power; Voltage Partitioning;
Conference_Titel :
Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA