Concurrent error detection scheme for HaF hardware

HaF (Hash Function) is a dedicated cryptographic hash function considered for verification of the integrity of data. It is suitable for both software and hardware implementation. HaF has an iterative structure. This implies that even a single transient error at any stage of the computation of hash value results in a large number of errors in the final hash value. Hence, detection of errors becomes a key design issue. In the hardware design of cryptographic algorithms, concurrent error detection (CED) techniques have been proposed not only to protect the encryption and decryption process from random faults but also from the intentionally injected faults by some attackers. In this paper, we show the propagation of errors in the VHDL model of HaF-256 and then we propose and analyse some error detection schemes. In proposed CED scheme all the components are protected and all single and multiple, transient and permanent bit flip faults will be detected.