DC-link current balancing and ripple reduction for direct parallel current-source converters

In high power applications, back-to-back (B2B) current-source converters (CSCs) in direct parallel connection results in topologies that allow for transformerless configuration and multilevel current waveforms. However, the unbalanced dc-link currents in steady state and the current ripples in transient are inevitable due to the tolerance of devices and the pulse width modulation (PWM) switching pulse, which involve different voltage-drops across the dc-link inductors. The unequal voltage-drops introduce the unbalanced currents and ripples. This paper presents a way to reduce the dc-link current ripples based on the steady-state current balancing control, which is implemented by proper selection of the redundant switching states and the sequence design. The essence of the strategy is to reduce the voltage-drops across the dc-link inductors, as well as the time invertal of the switching states that involve the same dc link. The control scheme for direct parallel CSCs is implemented based on multilevel space vector modulation (SVM) algorithm. The proposed concepts are verified by a 2MW/4160V Matlab/Simulink model.