Title :
Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis
Author :
Morvan, Antoine ; Derrien, Steven ; Quinton, P.
Author_Institution :
Inst. Nat. de Rech. en Inf. et en Autom., Rennes, France
Abstract :
High-level synthesis (HLS) allows hardware to be directly produced from behavioral description in C/C++, thus accelerating the design process. Loop pipelining is a key transformation of HLS, as it improves the throughput of the design at the price of a small hardware overhead. However, for small loops, its use often results in a poor hardware utilization due to the pipeline latency overhead. Overlapping the iterations of the whole loop nest instead of only overlapping the innermost loop is a way to overcome this difficulty, but currently available techniques are restricted to perfectly nested loops with constant bounds, involving uniform dependences only. Using the polyhedral model, we extend the applicability of the nested loop pipelining transformation by proposing a new legality check and a new loop correction technique, called polyhedral bubble insertion. This method was implemented in a source-to-source compiler targeting HLS, and results on benchmark kernels show that polyhedral bubble insertion is effective in practice on a much larger class of loop nests.
Keywords :
C++ language; high level synthesis; pipeline processing; program compilers; program control structures; C/C++; behavioral description; benchmark kernels; design process; hardware overhead; hardware utilization; high-level synthesis; innermost loop; legality check; loop correction technique; loop nests; nested loop pipelining transformation; perfectly nested loops; pipeline latency overhead; polyhedral bubble insertion; polyhedral model; source-to-source compiler targeting HLS; Arrays; Hardware; Indexes; Law; Pipeline processing; Schedules; Vectors; High-level synthesis (HLS); loop coalescing; nested loop pipelining; polyhedral model; source-to-source transformations;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2012.2228270