DocumentCode :
58174
Title :
Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation
Author :
Mohanty, Basant Kumar ; Meher, Pramod Kumar
Author_Institution :
Electron. & Commun. Eng., Jaypee Univ. of Eng. & Technol., Raghogarh, India
Volume :
8
Issue :
6
fYear :
2014
fDate :
Jun-14
Firstpage :
345
Lastpage :
353
Abstract :
Multiple lifting computation could be performed for block processing of two-dimensional (2D) discrete wavelet transform (DWT) by combined-lifting (CLF) or separated-lifting (SLF) approaches. CLF and SLF have the same computational complexities but they differ by their register requirements. In this study, the authors have chosen CLF for row processing and SLF for column processing, and suggested an efficient scheduling scheme for the computation of block-based lifting 2D DWT. Based on this approach, the authors have derived a parallel-pipeline structure for high-throughput implementation of one-level lifting 2D DWT. The authors have partitioned the multilevel 2D DWT computation appropriately and mapped that to a folded structure where the frame-buffer size is independent of input block size. The proposed structure requires 3N on-chip memory words, which is the lowest among all the existing similar structures. Compared with the best of the existing block-based structures for the one-level DWT, the proposed structure involves less on-chip memory words, requires the same number of multipliers and adders and offers the same throughput rate. The application specific integrated circuit (ASIC) synthesis result shows that the proposed structure involves significantly less area-delay-product and less energy per image than those of the best of the available designs.
Keywords :
application specific integrated circuits; data compression; discrete wavelet transforms; image coding; microprocessor chips; 3N on-chip memory words; ASIC synthesis; CLF; SLF; area-delay-power-efficient architecture; block processing; block-based lifting 2D DWT computation; column processing; combined-lifting approach; folded 2D discrete wavelet transform; frame-buffer size; image compression; input block size; multiple lifting computation; parallel-pipeline structure; register requirements; scheduling scheme; separated-lifting approach;
fLanguage :
English
Journal_Title :
Image Processing, IET
Publisher :
iet
ISSN :
1751-9659
Type :
jour
DOI :
10.1049/iet-ipr.2012.0661
Filename :
6838574
Link To Document :
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