A SET/MOS Hybrid Multiplier Using Frequency Synthesis

Author

Guoqing Deng ; Chunhong Chen

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada

Volume

21

Issue

9

fYear

2013

fDate

Sept. 2013

Firstpage

1738

Lastpage

1742

Abstract

This paper proposes a frequency synthesizer using single-electron transistor (SET)/MOS hybrid architectures for binary multiplier design. The main idea is to first convert the operands from their digital representation to frequency representation, and then perform multiplication in the frequency domain before converting the result back to the digital representation. The major merits of the proposed method include: 1) simplified implementation of binary multiplication and 2) high immunity against the background charges inherent in SET islands. Both circuit design and simulation are provided to show the effectiveness of the approach.

Keywords

MOSFET; frequency synthesizers; single electron transistors; SET-MOS hybrid multiplier; background charges; binary multiplication; binary multiplier design; circuit design; digital representation; frequency domain; frequency representation; frequency synthesis; frequency synthesizer; single-electron transistor-MOS hybrid architecture; Frequency modulation; Frequency synthesizers; Logic gates; MOSFETs; Oscillators; Radiation detectors; Frequency synthesis; SET/MOS hybrid architecture; multiplier; single-electron transistor (SET);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2012.2218264

Filename

6332537