DocumentCode :
58296
Title :
A 19 nm 112.8 mm 
64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface
Author :
Kanda, K. ; Shibata, Naotaka ; Hisada, Takashi ; Isobe, Keisuke ; Sato, Mitsuhisa ; Shimizu, Yukiyo ; Shimizu, Tsuyoshi ; Sugimoto, Taku ; Kobayashi, Takehiko ; Kanagawa, Naoki ; Kajitani, Y. ; Ogawa, Tomomi ; Iwasa, Koyo ; Kojima, Masaru ; Suzuki, Takumi
Author_Institution :
Toshiba Corp., Yokohama, Japan
Volume :
48
Issue :
1
fYear :
2013
fDate :
Jan. 2013
Firstpage :
159
Lastpage :
167
Abstract :
A 64 Gb MLC NAND flash memory in 19 nm CMOS technology has been developed. By adopting one-sided all bit line (ABL) architecture, the single cell array configuration, bit line bias acceleration (BLBA) and BC states first program algorithm, the smallest 64 Gb die size in 2 bit/cell is achieved with high performance of 15 MB/s program throughput. Program suspend and erase suspend functions are introduced to improve the read latency. High speed toggle mode interface of 400 Mbit/sec/pin at VCCQ = 1.8 V is also realized.
Keywords :
CMOS digital integrated circuits; flash memories; ABL architecture; BLBA; CMOS technology; MLC NAND flash memory; bit line bias acceleration; bit rate 15 Mbit/s; erase suspend functions; multilevel flash memory; one-sided all bit line architecture; program suspend functions; program throughput; read latency; single cell array configuration; size 19 nm; toggle mode interface; voltage 1.8 V; Acceleration; Ash; Computer architecture; Couplings; Latches; Microprocessors; Programming; BC state first program; NAND flash memory; Vth distribution; all bit line(ABL) architecture; cell-to-cell coupling effect; high-speed interface; read latency; resume; suspend;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2012.2215094
Filename :
6332543
Link To Document :
