Optimizing Simulation in Multiprocessor Platforms Using Dynamic-Compiled Simulation

Contemporary SoC design involves the proper selection of cores from a reference platform. Such selection implies the design exploration of CPUs, which requires simulation platforms with high performance and flexibility. Applying retarget able instruction-set simulation tools in this environment can simplify the design of new architectures. The increasing system complexity makes the traditional approach to simulation inefficient for today´s architectures. The dynamic-compiled instruction-set simulation compiles application code blocks, at runtime, to accelerate the simulation with high efficiency. This paper presents a retarget able dynamic-compiled simulator to improve the performance in multiprocessor platforms. Three architectures were modeled - MIPS, SPARC and PowerPC - and tested in platforms with 1, 2, 4 and 8 processors. The performance on platforms with dynamic-compiled simulators was 3 times better than interpreted simulators, using large programs. Dynamic-compiled simulators outside the platforms with single core programs reached the 139 Million Instructions per Seconds on average.