A Highly Scalable Butterfly-Based Photonic Network-on-Chip

Future chip multiprocessors will requires low-power, high performance on-chip networks. Photonic interconnects is a promising way to leverage silicon photonics for future CMPs. In this paper, we present a highly scalable BPNoC(butterfly-based photonic NoC). The most important feature of our proposed network is that it can scale to a more large size with acceptable performance by utilizing the characteristics of butterfly topology and basic photonic switching element (PSE2x2). BPNoC is a hierarchical network with an optical sub-network and an electrical sub-network. Optical sub-network with a load-balanced routing algorithm use circuit-based switching to transmit data packets, while the electronic sub-network with improved turn-around algorithm is based on packet-switching for control and data packet transmission. Finally, we analyze the optical loss, power consumption, and network performance for 64-core BPNoC under various synthetic traffic patterns. The results show that our proposed network has much low optical loss, good performance, and high energy efficiency.