An Efficient Hardware Random Number Generator Based on the MT Method

Mersenne Twister (MT) algorithm is one of the most widely used long-period uniform random number generators. In this paper, we present a novel and efficient hardware architecture for MT method. Our design is implemented on a Xilinx XC6VLX240T-1 FPGA device at 450 MHz. It takes up 0.1% of the device and produces 450 million samples per second, which is 2.25 times faster than a dedicated software version running on a 2.67-GHz Intel core i5 multi-core processor. A dedicated 3R/1W RAM structure is also proposed. It is capable of providing 3 reads and 1 write concurrently in a single clock cycle and is the key component for the entire system to achieve 1 sample-per-cycle throughput. The architecture is also implemented on different FPGA devices. Experimental results show that our generator is superior to those existing architectures reported in the literatures in both performance and hardware complexity. The samples generated by our design are verified via the standard statistics testing suites of Diehard and TestU01.