DocumentCode :
584257
Title :
Soft Error Issues with Scaling Technologies
Author :
Baeg, Sanghyeon ; Bae, Jongsun ; Lee, Soonyoung ; Lim, Chul Seung ; Jeon, Sang Hoon ; Nam, Hyeonwoo
Author_Institution :
Hanyang Univ., Seoul, South Korea
fYear :
2012
fDate :
19-22 Nov. 2012
Firstpage :
68
Lastpage :
68
Abstract :
As transistor geometry shrinks, the erroneous and spurious charge from a particle strike tends to be shared by multiple nodes and causes multiple nodes upset. Such SEU mechanism invalidates the hardening principle of protecting a single node in relatively larger technologies. SEU needs to be accordingly understood and evaluated. In an 28-nm design example, SEU can happen in 6-day interval if no mitigation technique is used.
Keywords :
geometry; radiation hardening (electronics); transistors; SEU mechanism; multiple nodes upset; particle strike; scaling technology; soft error issues; spurious charge; transistor geometry; Geometry; Market research; Mesons; Random access memory; Reliability; Single event upset; Transistors; multiple cell upset (MCU); single-event upset (SEU); soft error;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2012 IEEE 21st Asian
Conference_Location :
Niigata
ISSN :
1081-7735
Print_ISBN :
978-1-4673-4555-2
Electronic_ISBN :
1081-7735
Type :
conf
DOI :
10.1109/ATS.2012.72
Filename :
6394175
Link To Document :
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