Title :
Multi-level EDT to Reduce Scan Channels in SoC Designs
Author :
Li, Guoliang ; Qian, Jun ; Li, Peter ; Zuo, Greg
Author_Institution :
Adv. Micro Devices, Shanghai, China
Abstract :
This paper presents a new multi-level EDT scheme to reduce scan channels of scan-based SoC designs. Multi-level EDT requires trivial modification on existing EDT scheme with two-pass encoding. Experimental results show that this scheme can reduce channel count by up to 30% without penalty of test coverage and pattern count.
Keywords :
system-on-chip; channel count; embedded deterministic test; multilevel EDT scheme; scan based SoC design; scan channels; two pass encoding; Benchmark testing; Clocks; Encoding; Equations; Phase shifters; Ring generators; System-on-a-chip; Embedded Deterministic Test (EDT); multi-level EDT; reduce scan channels; scan-based testing; test data compression;
Conference_Titel :
Test Symposium (ATS), 2012 IEEE 21st Asian
Conference_Location :
Niigata
Print_ISBN :
978-1-4673-4555-2
Electronic_ISBN :
1081-7735
DOI :
10.1109/ATS.2012.70
