A Transition Isolation Scan Cell Design for Low Shift and Capture Power

Shift and capture power management has become indispensable for modern complex low-power designs. Excessive shift power increases test application time and may jeopardize the shift operation correctness, excessive capture power during at-speed scan testing may lead to yield loss. This paper proposes a scan cell design which isolates scan cells output transitions in both shift and capture modes. Experimental results on larger ISCAS´89, ITC´99, and IWLS´05 benchmark circuits show that the proposed scan cell design lowers capture power consumptions with reasonable CPU times and test set inflation.