DocumentCode :
584270
Title :
PowerMAX: Fast Power Analysis during Test
Author :
Zhao, Wei ; Tehranipoor, Mohammad
Author_Institution :
ECE Dept., Univ. of Connecticut, Storrs, CT, USA
fYear :
2012
fDate :
19-22 Nov. 2012
Firstpage :
227
Lastpage :
232
Abstract :
We present a fast power analysis flow called Power MAX in this paper. Power MAX is specially devised for power evaluation of test vectors. It has the capability of power calculation and peak current identification for each test cycle. This cycle-by-cycle power and current monitoring ensures the power-safety of test vectors before they are loaded to testers. Power MAX is layout-aware, thus able to pinpoint hotspots as well. The entire power analysis flow is seamlessly integrated into test vector simulation. Power MAX fills the gap of test power analysis flows that achieves both efficiency and accuracy. We believe our flow is the first attempt to address vector-based power evaluation problem especially for test mode. Results on industrial hard macros show that Power MAX provides high power-integrity sign-off accuracy with low CPU runtime.
Keywords :
automatic test pattern generation; vectors; CPU runtime; PowerMAX; current monitoring; cycle-by-cycle power; industrial hard macros; layout-aware; peak current identification; power calculation; power-integrity sign-off accuracy; power-safety; test cycle; test mode; test power analysis flows; test vector simulation; test vectors; vector-based power evaluation problem; Analytical models; Capacitance; Layout; Logic gates; Monitoring; Switches; Vectors; power analysis; power bumps; test power and power grid analysis; weighted switching activity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2012 IEEE 21st Asian
Conference_Location :
Niigata
ISSN :
1081-7735
Print_ISBN :
978-1-4673-4555-2
Electronic_ISBN :
1081-7735
Type :
conf
DOI :
10.1109/ATS.2012.60
Filename :
6394205
Link To Document :
بازگشت