DocumentCode :
584582
Title :
The Design and Implication of Multilevel FPGA Upgrade Online
Author :
Wang, Xiaohui ; Zhuang, Liyun ; Lu, Qing ; Tang, Yongfeng
Author_Institution :
Fac. of Electron. & Electr. Eng., Huaiyin Inst. of Technol., Huaiyin, China
fYear :
2012
fDate :
11-13 Aug. 2012
Firstpage :
2099
Lastpage :
2102
Abstract :
At present, the multilevel FPGA scheme is used widely in system for people life. In order to satisfy the need of product update, it is very urgent to find a way to solve the problem of Multilevel FPGA upgrade. The traditional method of single FPGA upgrade contains two steps, the first one is storing the configuration file to external NOR_FLASH; the second step is reading the file from external NOR_FLASH and configuring the FPGA. According to the traditional method, it would need more NORFLASH for each FPGA, which would not only increase the cost of product but also increase complexity of the circuit. So the traditional method was not suitable for multilevel FPGA upgrade. In order to solve the problem of multilevel FPGA upgrade online, it raised a scheme to implicate multilevel FPGA upgrade online. The design has been proved correct in SSD system. It also can be used in other system with the structure of multilevel FPGA.
Keywords :
field programmable gate arrays; flash memories; logic design; logic gates; multivalued logic circuits; SSD system; circuit complexity; configuration file; external NOR-FLASH; multilevel FPGA online upgrade; multilevel FPGA structure; product cost; Field programmable gate arrays; Hardware; Hardware design languages; IP networks; Load modeling; Loading; Timing; FPGA; SSD; cofiguration; upgrade;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Science & Service System (CSSS), 2012 International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4673-0721-5
Type :
conf
DOI :
10.1109/CSSS.2012.522
Filename :
6394840
Link To Document :
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