Title :
Co-analysis of signal and power integrity of 3D stacked package using flexible printed circuits
Author :
Ikemiya, Keisuke ; Kanazawa, Masato ; Sudo, Toshio ; Masuda, Shizuaki ; Hirakawa, Yasushi ; Wada, Kikuo
Author_Institution :
Shibaura-Inst. of Technol., Tokyo, Japan
Abstract :
Three dimensionally stacked package using FFCSP (Flexible carrier Folded real Chip Size Package) has been developed as one solution of high-density DRAM module. FPC (Flexible printed circuit) was effectively utilized to construct the pads at the both top and bottom sides of PoP (package-on-package) structure. In such multi-tiered package structures, the power supply stability for the upper tiered package is estimated to be worse than that of the lower tiered package due to parasitic inductance. In this paper, the co-analysis model including signal integrity (SI) and power integrity (PI) has been established to evaluate the power supply and signal quality among the multi-tiered chips. In particular, the power distribution networks (PDN) and eye diagrams for multi-tiered package were discussed.
Keywords :
DRAM chips; flexible electronics; integrated circuit packaging; power supply circuits; printed circuits; three-dimensional integrated circuits; 3D stacked package; FFCSP; FPC; PoP structure; coanalysis model; eye diagrams; flexible carrier folded real chip size package; flexible printed circuits; high-density DRAM module; lower tiered package; multitiered chips; multitiered package structures; package-on-package structure; parasitic inductance; power integrity; power supply stability; signal co-analysis; signal integrity; signal quality; three dimensionally stacked package; upper tiered package; DRAM chips; Impedance; Integrated circuit modeling; Noise; Power supplies; Solid modeling;
Conference_Titel :
Electromagnetic Compatibility (EMC EUROPE), 2012 International Symposium on
Conference_Location :
Rome
Print_ISBN :
978-1-4673-0718-5
DOI :
10.1109/EMCEurope.2012.6396881
