Schematic-driven physical verification: Fully automated solution for analog IC design

Designing ICs (integrated circuits) is inherently a complex task involving human expertise as well as aids intended to accelerate the process. A fundamental requirement for design success is a clear strategy that coordinates the entire design flow from specifications to a marketable product. Modem VLSI (very large scale integration) IC designs, especially analog/mixed signal LSIs, must meet various design and electrical constraints such as IR-drop, cross-talk, low power and low voltage design. This complexity poses several physical design challenges for specific analog structures such as device symmetry, net matching and more. Therefore it is essential to have some form of communication between the front-end designers (schematic and transistor level) and the physical layout engineers. The current process involves the front-end designer placing the design constraints in the form of annotations on the schematic netlist. These annotations are then passed to the layout team for manual implementation followed by visual verification only. This paper explores a new methodology providing a fully automated CAD flow that captures the designer´s intent from the schematic netlist, links these annotations to the proper devices or nets on the physical layout level, then runs verification checks using the Calibre ^R tool suite. Several applications can be used with the proposed flow, in this work we will present an application specifically for capturing design constraints related to physical layout recommendations, tested on Opamp circuit.