Title :
Multi-Clock DFT architecture for interface characterization and power
Author :
Ryan, Christopher ; Monsen, Kris ; Smith, Scott ; So, Henry
Abstract :
To address timing closure, interface characterization and power problems during test, a DFT architecture is presented for Multi-Clock designs. Results show that interface characterization is now able to be completed with ATPG, that test power is programmable, and that ATPG capture clock timing is unneeded. Current implementations include 65nm and 40nm Multi-Media Compression IC´s consisting of 18 to 46 clock domains, four to eight PLL´s, and several external interfaces.
Keywords :
automatic test pattern generation; clocks; design for testability; phase locked loops; timing circuits; ATPG; PLL; clock timing; interface characterization; interface power; multiclock DFT architecture; multimedia compression integrated circuit; power problems; programmable test power; size 40 nm; size 65 nm; timing closure; Automatic test pattern generation; Clocks; Discrete Fourier transforms; Integrated circuits; Phase locked loops; Synchronization;
Conference_Titel :
SOC Conference (SOCC), 2012 IEEE International
Conference_Location :
Niagara Falls, NY
Print_ISBN :
978-1-4673-1294-3
DOI :
10.1109/SOCC.2012.6398359
