A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation

Digital circuits have been traditionally designed to meet the worst PVT conditions to guarantee high yield. This design methodology produces an integrated circuit which has a big overhead in terms of area and power consumption in most of the cases. In this paper, a new better-than-worst-case-design methodology is proposed. It is based on a timing error speculation technique which features simple monitors located in the critical paths of the circuit that will speculate whether a timing error is going to occur or not. Using a 32-bit multiplier, this design methodology achieved area and power savings up to 50%, with 5% performance loss.