Variation-and-aging aware low power embedded SRAM for multimedia applications

This paper presents a low power embedded SRAM memory design for MPEG-4 video processors. Considering both of the process variation and aging effect, the proposed design adopts an optimal high voltage for spatial voltage scaling to achieve high power efficiency. Simulations in FreePDK 45nm CMOS technology show that our proposed technique can achieve 85%, 90%, and 79% reduction in write power, read power, and leakage current, respectively, with graceful degradation (~5.6%) in video quality, as compared to conventional SRAM design.