A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

Author

Seo, Jin-Cheol ; Im, Sang-Soon ; Yoon, Kwan ; Oh, Seung-Wook ; An, Taek-Joon ; Bae, Gi-Yeol ; Kang, Jin-Ku

Author_Institution

Dept. of Electron. Eng., Inha Univ. Incheon, Incheon, South Korea

fYear

2012

fDate

12-14 Sept. 2012

Firstpage

57

Lastpage

60

Abstract

In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7 and 5.4Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit employs a dual-loop architecture that includes a phase-locked loop and a frequency-locked loop. The circuit with a half-rate phase detector has a triple-mode voltage-controlled oscillator (VCO) which changes the operating frequency by 3bit code. The prototype chip is designed and verified using a 65nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4Gbps at 2³¹-1 PRBS is measured to 7/5.6/4.7ps_rms, respectively, while consuming 11mW with a 1.2V supply.

Keywords

CMOS integrated circuits; clock and data recovery circuits; frequency locked loops; integrated circuit noise; jitter; phase detectors; phase locked loops; voltage-controlled oscillators; CDR circuit; CMOS technology; DisplayPort 1.2 standard; VCO; bit rate 1.62 Gbit/s; bit rate 2.7 Gbit/s; bit rate 5.4 Gbit/s; clock and data recovery circuit; dual-loop architecture; frequency-locked loop; half-rate phase detector; phase-locked loop; power 11 mW; recovered-clock jitter; size 65 nm; triple data rate; triple-mode voltage-controlled oscillator; voltage 1.2 V; Clocks; Detectors; Frequency locked loops; Jitter; Phase locked loops; Standards; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference (SOCC), 2012 IEEE International

Conference_Location

Niagara Falls, NY

ISSN

2164-1676

Print_ISBN

978-1-4673-1294-3

Type

conf

DOI

10.1109/SOCC.2012.6398380

Filename

6398380