Title :
Evaluation of layout design styles using a quality design metric
Author :
Gómez, Sergio ; Moll, Francesc
Author_Institution :
Dept. of Electron. Eng., Univ. Politec. de Catalunya, Barcelona, Spain
Abstract :
Leading-edge chip makers are moving towards more regular litho-friendly design styles in order to combat litho-induced process variations. This paper explores layout design providing several layout templates and we propose a fast and simple design metric to evaluate the potential benefits and weaknesses of a given template. We show that a regular cell template can achieve similar overall qualification compared to a traditional 2D standard cell design.
Keywords :
integrated circuit layout; lithography; quality control; 2D standard cell design; layout design styles; leading-edge chip makers; litho-friendly design; litho-induced process variations; quality design metric; Layout; Lithography; Measurement; Reliability; Routing; Shape; Transistors; design metric; layout; lithography; regularity;
Conference_Titel :
SOC Conference (SOCC), 2012 IEEE International
Conference_Location :
Niagara Falls, NY
Print_ISBN :
978-1-4673-1294-3
DOI :
10.1109/SOCC.2012.6398396
