Title :
A stable chip-ID generating physical uncloneable function using random address errors in SRAM
Author :
Fujiwara, Hidehiro ; Yabuuchi, Makoto ; Tsukamoto, Yasumasa ; Nakano, Hirofumi ; Owada, Toru ; Kawai, Hiroyuki ; Nii, Koji
Author_Institution :
Renesas Electron. Corp., Tokyo, Japan
Abstract :
A stable chip-ID generating scheme using random failure bits in an SRAM array is proposed. Combining with a new screening test before shipping products, we realize high-tolerance against variability of operating condition. Measured data confirm that the stability and average of Hamming distance of 128 bit chip-ID achieve 100% and 63.7, respectively. The chip-ID generating time becomes less than 10us at 200 MHz operation.
Keywords :
SRAM chips; failure analysis; Hamming distance; SRAM array; frequency 200 MHz; high-tolerance; physical uncloneable function; random address errors; random failure bits; screening test; shipping products; stable chip-ID generating scheme; storage capacity 128 bit; Bit error rate; Hamming distance; Random access memory; Regulators; Semiconductor device measurement; Thermal stability; Voltage control;
Conference_Titel :
SOC Conference (SOCC), 2012 IEEE International
Conference_Location :
Niagara Falls, NY
Print_ISBN :
978-1-4673-1294-3
DOI :
10.1109/SOCC.2012.6398399
