An Efficient FPGA IP Core for Automatic Modulation Classification

This letter presents a new algorithm for automatic modulation classification (AMC) and its implementation and validation as an intellectual property (IP) core. AMC aims at accurately identifying the modulation scheme of a given communication system in a short period of time. The proposed IP core consists of a multiclass classifier composed by linear support vector machines and a new parameter extraction (front end) based on histograms. Based on its VHDL implementation and validation using FPGAs, the performance of the proposed system is compared with respect to accuracy and computational complexity to recently proposed AMC algorithms. The new AMC system does not require multipliers and achieves equivalent accuracy with respect to a baseline, while reducing by 50% and 90% the use of logic elements and memory, respectively.