Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

Author

Yan Zhu ; Chi-Hang Chan ; U-Fat Chio ; Sai-Weng Sin ; Seng-Pan U ; Martins, Rui P. ; Maloberti, Franco

Author_Institution

State-Key-Lab. Analog & Mixed-Signal VLSI, Univ. of Macau, Macao, China

Volume

22

Issue

2

fYear

2014

fDate

Feb. 2014

Firstpage

372

Lastpage

383

Abstract

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using Vcm-based switching.

Keywords

CMOS integrated circuits; analogue-digital conversion; logic design; shift registers; ADC; CMOS; DAC; SAR; analog-to-digital converters; charge-redistribution; differential nonlinearity; integral nonlinearity; linearity analysis; parasitic effects; power optimization; size 90 nm; speed optimization; successive approximation registers; switching methods; Arrays; Capacitance; Capacitors; Linearity; Standards; Switches; Very large scale integration; $V_{rm cm}$-based switching; Linearity analysis; SAR ADCs; linearity calibration; split DAC;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2013.2242501

Filename

6462023