Title :
A 107GHz LNA in 65nm CMOS with inductive neutralization and slow-wave transmission lines
Author :
Chuang Lu ; Mahmoudi, R. ; van Roermund, Arthur H. M. ; van Zeijl, Paul
Author_Institution :
Mixed-Signal Microelectron., Eindhoven Univ. of Technol., Eindhoven, Netherlands
Abstract :
This paper presents a 107GHz LNA prototype using TSMC 65nm CMOS technology. It explores the limit of the CMOS technology by effectively optimizing the active and passive devices. An improvement of 1.6dB higher maximum stable/available gain (MSG/MAG) on the transistor is achieved around 110GHz by layout optimization and inductor neutralization technique. A high quality factor co-planar waveguide (CPW) transmission line is designed utilizing the slow-wave effect. A quality factor of 23.6 is demonstrated by EM-simulations while taken the consideration of satisfying the stringent layout design rules. Based on the optimization on the active and passive devices, a dual-stage LNA is designed, with a simulated power gain of 10.2dB and noise figure of 8dB at 107GHz, verified by chip-level EM-simulations. The power consumption is 28.2mW.
Keywords :
CMOS integrated circuits; coplanar waveguides; field effect MIMIC; low noise amplifiers; millimetre wave amplifiers; transmission lines; CMOS technology; chip level EM simulations; coplanar waveguide transmission line; dual-stage LNA; frequency 107 GHz; gain 10.2 dB; inductive neutralization; layout design rules; layout optimization; low noise amplifiers; noise figure 8 dB; power 28.2 mW; quality factor; size 65 nm; slow-wave transmission lines; CMOS integrated circuits; CMOS technology; Gain; Inductors; Layout; Logic gates; Transistors;
Conference_Titel :
Communications and Vehicular Technology in the Benelux (SCVT), 2012 IEEE 19th Symposium on
Conference_Location :
Eindhoven
Print_ISBN :
978-1-4673-2114-3
Electronic_ISBN :
978-1-4673-2113-6
DOI :
10.1109/SCVT.2012.6399397
