Title :
Low power test application with selective compaction in VLSI designs
Author :
Czysz, D. ; Rajski, J. ; Tyszer, J.
Author_Institution :
Mentor Graphics Corp., Wilsonville, OH, USA
Abstract :
The paper presents an extended summary of the PhD thesis that tackles a low power decompression of test cubes in EDT environment and compaction of test responses in the presence of unknown states. The proposed low power decompression schemes allow one to reduce the load and unload switching activity by more than 93% and capture transitions by 52%. The X-masking scheme introduced in the thesis offers up to 48,000 x compression of control data, and eliminates all unknown states from test responses.
Keywords :
VLSI; data compression; integrated circuit design; integrated circuit testing; low-power electronics; EDT environment; VLSI designs; X-masking scheme; control data compression; low power decompression schemes; low power test application; test cubes; test response compaction; Circuit faults; Compaction; Encoding; Logic gates; Registers; Ring generators; Switches;
Conference_Titel :
Test Conference (ITC), 2012 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4673-1594-4
DOI :
10.1109/TEST.2012.6401532
