Algorithm for dramatically improved efficiency in ADC linearity test

For high performance analog and mixed-signal products, production test is a significant contributor to the recurring manufacturing cost. For high resolution ADCs, the cost of build can be dominated by test cost, of which linearity test cost is often the largest component. This paper introduces a new algorithm that dramatically reduces ADC linearity test cost. The algorithm takes a system identification approach using a segmented non-parametric model that captures both linear errors (mismatches, etc.) and truly nonlinear errors (voltage coefficients, etc.). By avoiding the gross inefficiencies inherent in conventional linearity test solutions, the new algorithm is able to reduce the required test data by a factor of over 100. The algorithm works for various types of ADCs, including SARs and pipelines. Simulation results and measurements against the gold standard servo-loop test validate the accuracy of the new solution. Results from multiple case studies involving both good and poor ADCs demonstrate that the new method achieved several times better precision than standard histogram test, while using two orders of magnitude less test data and hence test time.