Title :
Automated system level functional test program generation on ATE from EDA using Functional Test Abstraction
Author :
Ueda, Makoto ; Ishikawa, Seiichiro ; Goishi, M. ; Kitagawa, S. ; Araki, H. ; Inage, S.
Author_Institution :
ADVANTEST Corp., Gunma, Japan
Abstract :
This paper introduces new capability on System on a Chip (SoC) ATE, called "Functional Test Abstraction (FTA)", which allows us to execute an automatically generated system level functional test program from the system level design verification environment. The device under verification and device under test can be a complex SoC which has multiple logic time domains and multiple interfaces of the same or different types.
Keywords :
automatic test pattern generation; electronic design automation; integrated circuit testing; system-on-chip; ATE; EDA; FTA; SoC ATE; automated system level functional test program generation; complex SoC; device under test; device under verification; functional test abstraction; multiple logic time domains; system level design verification environment; system-on-chip; Hardware; Protocols; Synchronization; Time domain analysis; Universal Serial Bus; Vectors;
Conference_Titel :
Test Conference (ITC), 2012 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4673-1594-4
DOI :
10.1109/TEST.2012.6401590
