A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS

Author

Peiyuan Wan ; Wei Lang ; Rui Jin ; Chi Zhang ; Pingfen Lin

Author_Institution

Beijing Embedded Syst. Key Lab., Beijing Univ. of Technol., Beijing, China

fYear

2012

fDate

21-23 Nov. 2012

Firstpage

80

Lastpage

82

Abstract

A front-end unity-gain 1-bit flip-around DAC (FADAC) is exploited in a 12-bit opamp-sharing pipelined ADC, allowing a 1.8-V_pp full-swing input at a 1.1-V supply. The high input swing, coupled with a large feedback factor (≈1) of the FADAC, enables a low-voltage low-power design for a high resolution pipelined ADC. The prototype 12-bit ADC operating at 20-MS/s and 1.1-V supply achieves a 66.4 dB SNDR and 76.7 dB SFDR with a 3 MHz input. The ADC consumes 5.2 mW of power and occupies an active area of 0.44 mm² in 0.13-μm CMOS.

Keywords

CMOS analogue integrated circuits; circuit feedback; digital-analogue conversion; low-power electronics; operational amplifiers; pipeline processing; CMOS; FADAC; SFDR; SNDR; feedback factor; flip-around DAC; frequency 3 MHz; front-end unity-gain; high input swing; high resolution pipelined ADC; low-voltage low-power design; noise figure 66.4 dB; noise figure 76.7 dB; opamp-sharing pipelined ADC; power 5.2 mW; size 0.13 mum; voltage 1.1 V; voltage 1.8 V; word length 1 bit; word length 12 bit; CMOS integrated circuits; CMOS technology; Calibration; Capacitors; Gain; Power demand; Prototypes; Flip-around digital-to-analog converter (FADAC); low-power; low-voltage; opamp-sharing; pipelined analog-to-digital converter (ADC);

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology (RFIT), 2012 IEEE International Symposium on

Conference_Location

Singapore

Print_ISBN

978-1-4673-2303-1

Type

conf

DOI

10.1109/RFIT.2012.6401620

Filename

6401620