A 8.3–11.3GHz low cost integer-N synthesizer with 1.1° RMS phase error in 65nm CMOS

This paper presents a fully integrated low cost, low noise 10GHz synthesizer using 65nm RF CMOS process. The synthesizer provide low phase-noise and low reference spur, covering 8.3GHz to 11.3GHz using multiband low gain VCO with auto calibration for locking. The measured phase-noise of 9.75GHz is -77dBc/Hz at lKHz offset, -90.1dBc/Hz at 10KHz offset, -98.6dBc/Hz at 100KHz offset, and -112.5dBc/Hz at 1MHz offset, phase RMS jitter performance is to be less than 1.1° integrated from 1KHz to 1MHz, while maintaining 26MHz reference spur levels lowers -74.6dB cover the entire tuning range. The active die area is 0.55mm × 0.8mm. The chip operates over a wide range of supply voltage from 1.1 V to 1.3V and temperature from -40°C to +85°C respectively. The chip draws 31mA current with buffer from a +1.2V supply at +25°C.