DocumentCode :
587700
Title :
KL-cut based digital circuit remapping
Author :
Machado, L. ; Martins, Miguel ; Callegaro, Vinicius ; Ribas, Renato P. ; Reis, Andre I.
Author_Institution :
PGMICRO, UFRGS, Porto Alegre, Brazil
fYear :
2012
fDate :
12-13 Nov. 2012
Firstpage :
1
Lastpage :
4
Abstract :
This paper introduces the concept of k and kl-cuts on top of digital mapped circuits in netlist representations. Such new approach is derived from the concept of k and kl-cuts on top of And-Inverter Graphs (AIGs), respecting the differences between these two representations. The main motivation to use kl-cuts on top of mapped circuits is to perform local optimization. An algorithm for enumerating kl-feasible cuts on top of mapped circuits is proposed. A remapping approach is also presented. Preliminary results show that this approach is able to reduce up to 19% in area and up to 24% in delay of mapped circuits from a subset of ISCAS´85 benchmarks.
Keywords :
logic design; logic gates; ISCAS´85 benchmarks; and-inverter graphs; digital circuit remapping; digital mapped circuits; netlist representations; Benchmark testing; Delay; Inverters; Libraries; Logic gates; Optimization; AIG; cut enumeration; digital circuit; local optimization; remapping; resynthesis; technology mapping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
NORCHIP, 2012
Conference_Location :
Cpenhagen
Print_ISBN :
978-1-4673-2221-8
Electronic_ISBN :
978-1-4673-2222-5
Type :
conf
DOI :
10.1109/NORCHP.2012.6403106
Filename :
6403106
Link To Document :
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