A low-power methodology for configurable wide kogge-stone adders

We propose a methodology to reconfigure a wide Kogge- Stone (KS) adder that is typically used in multimedia applications in order to minimize its power-delay product. The goal of the methodology is to enable the designer to select the best configuration to meet specifications in terms of power consumption, delay, and area. We measure the variations of these metrics by investigating several combinations of smaller KS adders connected in a ripple carry architecture. We test various adder combinations by performing HSPICE simulations in 90nm static CMOS. The results show that a designer can choose among different adder architectures to achieve different objectives.