TSVs macro-modeling framework

Author

Salah, Khaled ; Rouby, A.E. ; Ragai, Hani ; Ismail, Yousr

Author_Institution

Mentor Graphics, Cairo, Egypt

fYear

2011

fDate

Nov. 30 2011-Dec. 2 2011

Firstpage

1

Lastpage

4

Abstract

Modeling parasitic parameters of Through-Silicon Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3-D) Integrated Circuits (ICs). This paper presents a complete set of selfconsistent equations including self and coupling terms for capacitance of general multi-TSV structures. The error when using the closed form expressions as compared to a field solver is less than 7%. As TSV parasitic capacitance is less than other conventional IO structures´ capacitance, therefore TSV technology results in lower I/O power consumption which makes it suitable for low power applications.

Keywords

integrated circuit interconnections; integrated circuit modelling; low-power electronics; three-dimensional integrated circuits; 3D IC interconnections; I-O power consumption; IO structure capacitance; TSV macro-modeling framework; TSV parasitic capacitance; circuit delay; electrical characteristics; general multiTSV structures; low-power applications; parasitic parameter modeling; signal integrity; three-dimensional integrated circuits; through-silicon via structures; Capacitance; Couplings; Integrated circuit interconnections; Integrated circuit modeling; Mathematical model; Solid modeling; Through-silicon vias; Dimensional Analysis; Macro-Modeling; Modeling; TSV; Three-Dimensional ICs; Through Silicon Via;

fLanguage

English

Publisher

ieee

Conference_Titel

Energy Aware Computing (ICEAC), 2011 International Conference on

Conference_Location

Istanbul

Print_ISBN

978-1-4673-0466-5

Electronic_ISBN

978-1-4673-0464-1

Type

conf

DOI

10.1109/ICEAC.2011.6403632

Filename

6403632