Title :
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems
Author :
Meloni, Paolo ; Pomata, S. ; Raffo, Luigi ; Piscitelli, R. ; Pimentel, Andy D.
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Cagliari, Cagliari, Italy
Abstract :
Modern heterogeneous multi-processor embedded systems very often expose to the designer a large number of degrees of freedom, related to the application partitioning/mapping and to the component- and system-level architecture composition. The number is even larger when the designer targets systems based on configurable Application Specific Instruction-set Processors, due to the fine customizability of their internal architecture. This poses the need for effective and user-friendly design tools, capable to deal with the extremely wide system-level design space exposed by multi-processor architecture and, at the same time, with an extended variety of processing element architectural configurations, to be evaluated in detail and in reasonable times. As a possible solution, within the MADNESS project [1], an integrated toolset has been proposed, combining the benefits of novel fast FPGA-based prototyping techniques with those provided by high-level simulation. In the toolset, the resulting evaluation platform serves as an underlying layer for a Design Space search algorithm. The paper presents the individual tools included in the toolset and their interaction strategy. The approach is then evaluated with a design space exploration case study, taking as a target application a video compression kernel. The integrated toolset has been used to produce a Pareto front of evaluated system-level configurations.
Keywords :
data compression; embedded systems; field programmable gate arrays; multiprocessing systems; video coding; FPGA-based prototyping technique; MADNESS project; application mapping; application partitioning; application specific instruction-set processor; evaluated system-level configuration; field programmable gate array; heterogeneous multiprocessor embedded system; high-level simulation; multiASIP system; on-hardware prototyping; system-level architecture composition; system-level design space; video compression kernel; Computational modeling; Computer architecture; Field programmable gate arrays; Program processors; Registers; Search engines; Space exploration;
Conference_Titel :
Embedded Computer Systems (SAMOS), 2012 International Conference on
Conference_Location :
Samos
Print_ISBN :
978-1-4673-2295-9
Electronic_ISBN :
978-1-4673-2296-6
DOI :
10.1109/SAMOS.2012.6404191