• DocumentCode
    588124
  • Title

    IR-drop reduction in sub-VT circuits by de-synchronization

  • Author

    Karlsson, Anders ; Andersson, Oskar ; Sparso, J. ; Rodrigues, Joachim Neves

  • Author_Institution
    Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden
  • fYear
    2012
  • fDate
    9-10 Oct. 2012
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    This paper proposes IR-drop reduction of sub-VT circuits by de-synchronization. The de-synchronization concept is briefly demonstrated and analyzed by a case study. Extensive IR-drop analysis´ of various technology options of a 65 nm CMOS family demonstrate how the noise margins are reduced due to switching noise on the supply rails. It is shown that a de-synchronized implementation reduces severe voltage drops on the supply rails by approximately 50%, compared to a clocked design.
  • Keywords
    CMOS logic circuits; asynchronous circuits; circuit noise; logic design; CMOS; IR-drop reduction; asynchronous circuit design; desynchronization; size 65 nm; subVT circuit; switching noise; voltage drop reduction; Libraries; Logic gates; Noise; Rails; Registers; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Subthreshold Microelectronics Conference (SubVT), 2012 IEEE
  • Conference_Location
    Waltham, MA
  • Print_ISBN
    978-1-4673-1586-9
  • Type

    conf

  • DOI
    10.1109/SubVT.2012.6404303
  • Filename
    6404303
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=588124