Sub-VT design of a wake-up receiver back-end in 65 nm CMOS

In sensor network applications, the use of duty-cycled ultra-low power wake-up receivers can significantly reduce overall power consumption. An important complement to previous investigations is to show that low-power wake-up receivers with good enough detection performance can be realized in hardware. In this paper we address this very issue by presenting the design, implementation, and sub-VT characterization of a digital back-end for such an ultra-low power WRx.