DocumentCode :
588160
Title :
High voltage SOI MESFETs at the 45nm technology node
Author :
Lepkowski, William ; Wilk, Seth J. ; Ghajar, M.R. ; Thornton, Trevor J.
Author_Institution :
Arizona State Univ., Tempe, AZ, USA
fYear :
2012
fDate :
1-4 Oct. 2012
Firstpage :
1
Lastpage :
2
Abstract :
Enhanced voltage SOI MESFETs have been demonstrated on a highly scaled CMOS process. Their DC and RF performance along with reproducibility suggests that they would be ideal in a variety of analog and PA applications. Also, since they can be fabricated alongside the 45nm CMOS [4], they appear suitable for system-on-chip applications as an interface between high voltage external devices and the low voltage CMOS. While these initial results are encouraging, new MESFET geometries and structures have been taped out to further enhance the breakdown voltage. Lastly, with continued layout optimization it is expected that the variance between devices will be reduced.
Keywords :
CMOS integrated circuits; Schottky gate field effect transistors; silicon-on-insulator; DC performance; RF performance; breakdown voltage enhancement; enhanced voltage SOI MESFET; high voltage SOI MESFET; high voltage external devices; highly scaled CMOS process; layout optimization; low voltage CMOS; size 45 nm; system-on-chip applications; CMOS integrated circuits; CMOS technology; Logic gates; MESFETs; Stress; Threshold voltage; Voltage measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference (SOI), 2012 IEEE International
Conference_Location :
NAPA, CA
ISSN :
1078-621X
Print_ISBN :
978-1-4673-2690-2
Electronic_ISBN :
1078-621X
Type :
conf
DOI :
10.1109/SOI.2012.6404403
Filename :
6404403
Link To Document :
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