A High-Speed SHA-1 IP Core for 10 Gbps Ethernet Security Processor

10Gbps Ethernet Security Processor is very important in future network telecommunication. In order to meet the performance of ultra high throughput of 10Gbps ESP, An architecture of multiple SHA-1 IP cores paralleled based crossbar switch are proposed in this paper. Firstly, An ultra high throughput, low power consumption SHA-1 algorithm IP-core are designed, then, an effective scheduling architecture with SHA-1 IP cores are proposed in this paper. In our simulation with SMIC 65nm, the throughput of single IP core could reach to 4.27Gbps in the frequency of 400Mhz. Verification are based on Xilinx Virtex FPGA, 1943 slices LUTs are used for each SHA-1 IP core. By using this crossbar architecture, the number of SHA-1 IP cores used in 10Gbps Network Security Processor could decrease to four, which decrease the total area and power consumption of Network Security Processor significantly.