Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface

Author

Woorham Bae ; Byoung-Joo Yoo ; Deog-Kyoon Jeong

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea

fYear

2012

fDate

4-7 Nov. 2012

Firstpage

49

Lastpage

52

Abstract

A 5Gb/s four-level pulse amplitude modulation (4-PAM) transceiver front-end for low-power memory interface is proposed. Since the most power-consuming blocks in high-speed link front-end are drivers, and equalizers, in this work, we have used 4-PAM voltage mode driver to reduce the power consumption of driver and equalizer. Moreover, an analysis to minimize voltage mode driver power consumption is presented. In order to eliminate the reflection in a multi-drop bus, an impedance-matched bi-directional multi-drop bus has implemented. Simulation results show the proposed transceiver front-end has power efficiency of 1.7 mW/Gbps. Circuit design and simulation were done in 0.13-μm CMOS technology.

Keywords

CMOS memory circuits; driver circuits; integrated circuit design; low-power electronics; pulse amplitude modulation; transceivers; 4-PAM voltage mode driver; CMOS 4-PAM transceiver frontend design; CMOS four-level pulse amplitude modulation transceiver front-end; bit rate 5 Gbit/s; equalizer; high-speed link front-end; low-power memory interface; multidrop bus; power-consuming blocks; size 0.13 mum; voltage mode driver power consumption; CMOS integrated circuits; CMOS technology; Equalizers; Power demand; Reflection; Solid state circuits; Transceivers; 4-PAM; CMOS; IMBM; Transceiver front-end; low-power; memory interface; voltage mode driver;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2012 International

Conference_Location

Jeju Island

Print_ISBN

978-1-4673-2989-7

Electronic_ISBN

978-1-4673-2988-0

Type

conf

DOI

10.1109/ISOCC.2012.6406922

Filename

6406922