Low-latency area-efficient decoding architecture for shortened reed-solomon codes

The shortened RS code is traditionally decoded based on the standard decoding process by padding zero symbols. As additional cycles are redundantly taken to deal with the zero symbols, the processing latency of the shortened code is almost the same as that of the mother RS code from which the shortened code is derived. A new architecture is proposed in this paper to decrease the processing latency to the codeword length of the shortened RS code, which can be implemented at the cost of small additional hardware resources. The additional hardware complexity is minimized by reutilizing the hardware resources resident in the adjacent block. Experimental results show that the proposed method leads to a significant reduction of the overall latency. For the RS (32, 24) code, the overall processing latency is reduced by 85.2% and 33.6% compared to the conventional and the previous work, respectively. Moreover, the additional hardware complexity of the proposed method is smaller than those of the previous architectures.