Title :
A 516Mb/s 0.2nJ/bit/iter variable-block-size turbo decoder for 3GPP LTE-A system
Author :
Chi-Hsuan Hsieh ; Ming-Yong Lee ; Yuan-Hao Huang
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
Abstract :
This paper presents a high-throughput turbo decoder supporting 188 block sizes for 3GPP LTE-Advanced system. This study investigates the memory contention problem when the turbo decoder has none-power-of-two degree of parallelism of MAP processors. The proposed method aims to reduce unnecessary MAP processors when 2n MAP processors costs too much for a targeted throughput rate. The turbo decoder achieves a throughput of 516Mb/s for 6144-bit block after 4 iterations with 0.2nJ/bit/iteration energy efficiency using a 90nm CMOS technology.
Keywords :
3G mobile communication; Long Term Evolution; codecs; turbo codes; 3GPP LTE-A system; CMOS technology; MAP processor; bit rate 516 Mbit/s; size 90 nm; variable block-size turbo decoder; Algorithm design and analysis; Computer architecture; Decoding; Measurement; Parallel processing; Program processors; Throughput;
Conference_Titel :
SoC Design Conference (ISOCC), 2012 International
Conference_Location :
Jeju Island
Print_ISBN :
978-1-4673-2989-7
Electronic_ISBN :
978-1-4673-2988-0
DOI :
10.1109/ISOCC.2012.6407111
