A low-power high-gain 2.45-GHz CMOS dual-stage LNA with linearity enhancement

Author

Eshghabadi, Farshad ; Eshghabadi, H.A. ; Noh, Norlaili Mohd ; Mustaffa, Mohd Tafir ; Manaf, Asrulnizam Abd ; Sidek, Othman

Author_Institution

Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Nibong Tebal, Malaysia

fYear

2012

fDate

3-4 Oct. 2012

Firstpage

249

Lastpage

253

Abstract

This paper presents a dual-stage LNA design which is enhanced for gain, linearity and noise figure under a certain power constraint. The LNA benefits from an inductively-degenerated cascode amplifier in the first stage which is followed by a common-source amplifier as the second stage. Two techniques are used to improve the linearity of this 24-dB gain LNA while maintaining the noise figure equal to 2 dB. An input 1-dB gain compression point of -21 dBm was achieved at 2.45-GHz operating frequency. The 0.13-μm CMOS LNA draws a 4-mA current from a 1.2-volt power supply.

Keywords

CMOS analogue integrated circuits; UHF amplifiers; low noise amplifiers; CMOS LNA; cascode amplifier; common source amplifier; current 4 mA; dual stage LNA design; frequency 2.45 GHz; gain 1 dB; gain 24 dB; gain compression; linearity enhancement; low power high gain CMOS; noise figure; noise figure 2 dB; size 0.13 mum; voltage 1.2 V; CMOS integrated circuits; Gain; Impedance matching; Linearity; Noise; Noise figure; CMOS; Cascode; LNA; Linearity; PCSNIM;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ICCAS), 2012 IEEE International Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4673-3117-3

Electronic_ISBN

978-1-4673-3118-0

Type

conf

DOI

10.1109/ICCircuitsAndSystems.2012.6408333

Filename

6408333