Title :
Design of low noise and fast lock PLL by using switch matrix
Author_Institution :
Tianjin Jinhang Inst. of Comput. Technol., Tianjin Univ., Tianjin, China
Abstract :
A PLL frequency synthesizer is designed by using switch matrix and mixer, in order to reduce the phase noise and lock time. Using of bandwidth optimize, mixer, low noise VCO, and low noise crystal oscillator to optimize the system phase noise and also reduce the lock time. Switch matrix is used to reduce the spur and lock time. Test shows that the output phase noise is -151dBc@10kHz.
Keywords :
crystal oscillators; frequency synthesizers; mixers (circuits); phase locked loops; phase noise; voltage-controlled oscillators; PLL frequency synthesizer; frequency 10 kHz; lock time reduction; low-noise VCO; low-noise crystal oscillator; low-noise fast-lock PLL design; mixer; phase noise reduction; spur reduction; switch matrix; Bandwidth; Crystals; Mixers; Phase locked loops; Phase noise; Switches; Voltage-controlled oscillators; PLL; bandwith; lock time; phase noise; switch matrix;
Conference_Titel :
Antennas, Propagation & EM Theory (ISAPE), 2012 10th International Symposium on
Conference_Location :
Xian
Print_ISBN :
978-1-4673-1799-3
DOI :
10.1109/ISAPE.2012.6408988
