A 143dB 1.96% FPN linear-logarithmic CMOS image sensor with threshold-voltage cancellation and tunable linear range

This paper presents a high dynamic range (DR) linear-logarithmic (Lin-Log) CMOS image sensor (CIS) pixel with on-chip tunable linear range and threshold voltage cancellation scheme for reducing fix pattern noise (FPN). A column shared-OP with programmable gain was also applied to reduce the gain loss of source follower in conventional APS structure. A prototype chip with 100 × 100 pixel array and pixel pitch as 6 × 6 um² and 3.3V operation has been designed and fabricated in 0.18um TSMC 1P6M standard process. The measured results achieve a dynamic range of 143dB, a FPN related to sensitivity in log response (rms/log-sensitivity) of 1.96%, and a FPN related to full-swing in log response (rms/V_log-swing) of 0.45%, respectively.