A 143dB 1.96% FPN linear-logarithmic CMOS image sensor with threshold-voltage cancellation and tunable linear range

Author

Wei-Fan Chou ; Shang-Fu Yeh ; Chih-Cheng Hsieh

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2012

fDate

28-31 Oct. 2012

Firstpage

1

Lastpage

4

Abstract

This paper presents a high dynamic range (DR) linear-logarithmic (Lin-Log) CMOS image sensor (CIS) pixel with on-chip tunable linear range and threshold voltage cancellation scheme for reducing fix pattern noise (FPN). A column shared-OP with programmable gain was also applied to reduce the gain loss of source follower in conventional APS structure. A prototype chip with 100 × 100 pixel array and pixel pitch as 6 × 6 um² and 3.3V operation has been designed and fabricated in 0.18um TSMC 1P6M standard process. The measured results achieve a dynamic range of 143dB, a FPN related to sensitivity in log response (rms/log-sensitivity) of 1.96%, and a FPN related to full-swing in log response (rms/V_log-swing) of 0.45%, respectively.

Keywords

CMOS image sensors; FPN linear-logarithmic CMOS image sensor; TSMC 1P6M standard process; column shared-OP; fix pattern noise linear-logarithmic CMOS image sensor; high DR Lin-Log CIS pixel; high dynamic range linear-logarithmic CMOS image sensor pixel; on-chip tunable linear range scheme; pixel array; pixel pitch; programmable gain; size 0.18 mum; source follower gain loss; threshold voltage cancellation scheme; tunable linear range; voltage 3.3 V; Arrays; CMOS image sensors; Dynamic range; Semiconductor device measurement; Sensitivity; System-on-a-chip; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Sensors, 2012 IEEE

Conference_Location

Taipei

ISSN

1930-0395

Print_ISBN

978-1-4577-1766-6

Electronic_ISBN

1930-0395

Type

conf

DOI

10.1109/ICSENS.2012.6411258

Filename

6411258