Title :
A V-band CMOS frequency quadrupler with 3-dBm output power
Author :
Jhu-Rong Syu ; Kun-Yao Kao ; Kun-You Lin
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A V-band frequency quadrupler implemented in 90-nm LP CMOS process is proposed with 3-dBm output power. This frequency quadrupler consists of a 30-GHz frequency doubler, a 30-GHz buffer amplifier and a 60-GHz frequency doubler. The measured maximum conversion gain is 3 dB at 66 GHz, and the 3-dB bandwidth is from 62 to 70 GHz under 0-dBm input drive power. Harmonic suppressions of the fundamental, the second and the third harmonics are all better than 30 dB. The dc power consumption is 53.4 mW, and the chip size is 0.57 × 0.59 mm2.
Keywords :
CMOS analogue integrated circuits; amplifiers; buffer circuits; frequency multipliers; harmonics suppression; LP CMOS process; V band CMOS frequency quadrupler; V band frequency quadrupler; buffer amplifier; dc power consumption; frequency 30 GHz; frequency 60 GHz; frequency 62 GHz to 70 GHz; frequency doubler; gain 3 dB; harmonic suppression; output power; power 53.4 mW; size 90 nm; CMOS integrated circuits; Gain; Harmonic analysis; Harmonics suppression; Power amplifiers; Power generation; Power harmonic filters; CMOS; V-band; doubler; quadrupler;
Conference_Titel :
Microwave Conference Proceedings (APMC), 2012 Asia-Pacific
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1330-9
Electronic_ISBN :
978-1-4577-1331-6
DOI :
10.1109/APMC.2012.6421545
