DocumentCode :
591439
Title :
Design of high delay block using voltage scaling technique
Author :
Chaudhuri, Chandrima ; Kumar, Vipin ; Ghosh, Narendra Nath ; Mal, A.K.
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Durgapur, India
fYear :
2012
fDate :
28-29 Dec. 2012
Firstpage :
457
Lastpage :
460
Abstract :
Delay blocks are an important building block of signal processing circuits. To a great extent, performance of such circuits depend on the efficient design of delay blocks. In this work, a new scheme for designing a high delay chain is presented precisely for low frequency applications. The proposed design is based on the fact that propagation delay of a CMOS inverter increases with scaling down of supply voltage. This technique is highly area and power efficient as compared to other commonly used techniques. Designing of Ring Oscillator and Non-Overlapping-Clock (NOC) generator with the proposed scheme is also demonstrated. Designs are simulated on UMC 180 nm CMOS process with 1.8 V supply. Simulation results presented here strongly support the analysis done throughout the work. It is also shown that as the frequency of operation reduces, the proposed scheme becomes more and more advantageous. PVT analysis confirm the rigidity of the architecture.
Keywords :
CMOS integrated circuits; invertors; oscillators; CMOS inverter; NOC generator; PVT analysis; delay block; high delay chain; low frequency application; nonoverlapping-clock; propagation delay; ring oscillator; signal processing circuit; size 180 nm; voltage 1.8 V; voltage scaling technique; CMOS integrated circuits; Clocks; Delay; Generators; Inverters; Propagation delay; Ring oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Devices and Intelligent Systems (CODIS), 2012 International Conference on
Conference_Location :
Kolkata
Print_ISBN :
978-1-4673-4699-3
Type :
conf
DOI :
10.1109/CODIS.2012.6422237
Filename :
6422237
Link To Document :
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