Sparse Matrix-Vector Multiplication Based on Network-on-Chip: On Data Mapping

Sparse Matrix-Vector Multiplication (SMVM) on parallel hardware is a very sophisticated problem because of the irregular data communication requirements. The communication volume in the parallel hardware is determined by how data is distributed among the processing elements. In this paper we introduce two methods of data mapping for SMVM based on Network-on-Chip (NoC) in order to spread the load among its components. Later, we introduce the effect of reordering of the sparse matrix on those mapping methods. Simulations are performed using an OMNeT++ based NoC simulator.